Our Mission

At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you’re ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you’re in the right place.

Who We Are

In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values: Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real-world problems and ideating beside the best and the brightest, we invite you to join us!

We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes.

Job Summary

About the Role

We are seeking a highly skilled and motivated Senior to Principal EDVT Engineer to join our hardware engineering team. In this role, you will lead the end-to-end design verification, validation, and testing of complex electronic systems, high-speed interfaces, and power delivery networks. You will be instrumental in bridging the gap between hardware design and mass production, ensuring our products meet the highest standards of signal integrity, power integrity, and regulatory compliance.

If you thrive in a fast-paced environment, love troubleshooting complex hardware anomalies, and want to own the verification strategy for next-generation hardware, we want to hear from you.

Key Responsibilities

Test Strategy & Execution: Lead the development, execution, and optimization of EDVT test plans for complex circuit boards (PCAs) and full-system hardware.
Signal & Power Integrity: Perform rigorous hands-on validation of high-speed interfaces (e.g., PCIe, USB, DDR, I2C, SPI) and power delivery networks (DC-DC converters, ripple, transient response).
Cross-Functional Collaboration: Partner closely with Hardware Design, Signal Integrity (SI), Firmware, and Component Quality teams to root-cause design issues and validate fixes.
Lab Automation: Design and implement automated test setups using Python or LabVIEW to increase test coverage, repeatability, and efficiency.
Failure Analysis: Utilize advanced lab equipment to debug complex hardware anomalies, component failures, and unexpected system behaviors during EVT and DVT phases.
NPI & Manufacturing Support: Collaborate with contract manufacturers (CMs) and Joint Development Manufacturers (JDMs) to transition products from prototype to mass production.

Documentation: Author comprehensive test reports, white papers on critical design bugs, and validation summaries for executive and engineering review.

Qualifications

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Experience: 5+ years of hands-on experience in electronic product validation, EDVT, or hardware design engineering.
Technical Mastery: Deep understanding of hardware architecture, schematic design reading, and PCB layouts.
Lab Expertise: Expert-level proficiency with high-speed digital oscilloscopes, spectrum analyzers, protocol analyzers, logic analyzers, and digital multi-meters (DMMs).
Automation: Strong scripting skills in Python (or similar languages) for test automation and data analysis.
Problem Solving: Proven track record of debugging complex physical-layer and system-level issues under tight timelines.
Communication: Exceptional verbal and written communication skills, with the ability to distill complex technical findings into actionable insights for cross-functional teams.

Preferred Qualifications

Experience with automated test frameworks and data visualization tools.
Familiarity with environmental testing (Thermal, Shock/Vibe) and compliance standards (EMI/EMC, Safety).
Experience managing or guiding junior test engineers or technicians.

Why Join Us?

Impact: You will have direct ownership of product quality and reliability for cutting-edge technology.
Culture: A collaborative, engineering-first environment where continuous learning and innovation are celebrated.
Growth: Opportunities to expand your scope into hardware architecture, advanced signal integrity simulation, or engineering leadership.

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/com-missioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here.

$143,100.00 - $231,475.00/yr

Our Commitment

We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations@paloaltonetworks.com.

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

All your information will be kept confidential according to EEO guidelines.

Is role eligible for Immigration Sponsorship?: Yes

Senior Hardware Test Engineer (EDVT Engineer Hardware)