About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

This is an existing vacancy.

Your Team, Your Impact

As a Digital IC Design Senior Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

As a Senior Principal Design Engineer, you will contribute to chip architectures and lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for custom AI/HPC Hyperscaler customer needs.

Additional responsibilities will include, but not be limited to:

Investigate, scope and plan new AI/HPC SOC programs
Define ASIC and/or block architecture, micro-architecture and register specification. Participate and drive specification writeup
Conduct detailed architectural and/or design requirement reviews with customers, cross-functional teams, IP Vendors
Lead and execute the implementation of a specification based on RTL coding techniques and best practices
Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff.
Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation, performance analysis and debug
Help develop and/or evaluate design and verification methodologies and participate in improving existing ones
Provide mentorship to the more junior team members

What We're Looking For

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.

Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience.

The candidate must possess demonstrated work experience in the following areas:

Creating architectural and micro-architectural specifications
Verilog/System Verilog RTL coding with System Verilog Assertions
Well versed in design and leadership of all stages of the ASIC design flow (including specification, architecture, and design implementation)
Expertise in any of the following domains would be a big plus: Computer Architecture, Embedded Systems Architecture, Networking, Machine Learning Accelerators
Experience with scripting in Perl/Python/Shell

Expected Base Pay Range (CAD)

170,300 - 227,100, $ per annum

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.

#LI-JT2

Senior Principal IC Design Engineer, AI/HPC