Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, our innovative microinverter technology revolutionized solar power, making it a safer, more reliable, and scalable energy source. Today, the Enphase Energy System enables users to make, use, save, and sell their own power. Enphase is also one of the most successful and innovative clean energy companies in the world, with more than 80 million products shipped across 160 countries.

Join our dynamic teams designing and developing next-gen energy technologies and help drive a sustainable future!

This role at Enphase requires working onsite 3 days a week, with plans to transition back to a full 5 day in office schedule over time.

About the Role

Enphase is looking for an experienced SoC and IP Subsystems design engineer to work on our next generation CPU subsystem or peripheral IP development and integration. The MCU will use the ARM CM4 core, so experience with that core is a must. We will also be integrating safety and security features into this next generation of MCU so a deep understanding of these SoC challenges is required. This position is in our ASIC Engineering Team - Bangalore, reporting to the Senior Director of ASIC engineering.

What you will be doing
Working with our Architects you will architect, design and integrate our CPU Subsystem or peripheral Ips into our next generation of MCUs. Including the safety and security features that are required by our applications. You will be responsible for defining the verification plans for these subsystems.

Who you are and What you bring
Deep understanding and experience in SoC micro architecture, IP Development, RTL and integration.
Specific experience integrating the ARM CM4 and all the surrounding IP, like: AHB, AXI, RAM and ROM controllers, DMA controllers. As our MCUs include security features, experience with the ARM Protection units is preferred. Experience with one of the “TrustZone” like IP from other vendors will be an added avdavntage. As the Control ASICs from Enphase contain a large AFE, experience with integrating high speed and high accuracy analog systems is a must. RTL Integration of SoC/Subsystems from IPs, ability to debug the issues in logic verification, act as liaison between Design and Place and Route teams is mandatory.

Knowledge of all the Soft IP collateral and deliverables eg: Lint, CDC, UPF, timing constraints.
Experience and ability to shape and direct our future IP and SoC integration methodology.

Principal Engineer, RTL Design