About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Center of Excellence (COE), part of the Custom Compute and Storage (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems — spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies — that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle — sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.

What You Can Expect

Responsibilities include:

Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems, from test planning through coverage closure and signoff
Define and execute comprehensive verification plans based on protocol specifications and micro-architecture requirements
Architect and develop scalable UVM/System Verilog testbenches for PCIe/CXL controllers and fabric-level subsystems
Integrate and configure PCIe/CXL VIP for subsystem and system-level verification environments
Validate CXL.io, CXL.cache, and CXL.mem protocols, including coherency and memory semantics across complex flows
Develop constrained-random and directed test suites to achieve high functional coverage across corner and stress scenarios
Debug complex failures such as protocol violations, ordering issues, and coherency bugs using waveforms, logs, and protocol analyzers
Implement System Verilog Assertions (SVA) for protocol compliance, improving early bug detection and debug efficiency
Drive functional, code, and assertion coverage closure, identifying gaps and developing targeted tests to meet signoff goals
Validate performance metrics (latency, throughput, QoS) under high-bandwidth and stress workloads
Develop automation (Python/Shell) for regression management, log triage, and coverage reporting, improving productivity
Collaborate with design, architecture, firmware and validation teams, influencing design-for-verification and mentoring junior engineers

What We're Looking For

Required Qualifications:

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field
5-10 years of experience in ASIC/SoC verification
Strong knowledge of PCIE and CXL protocols and architecture
Expertise in System Verilog and UVM methodology
Experience with debugging complex verification issues
Familiarity with industry-standard tools (e.g., simulation, waveform debugging, coverage tools)
Solid understanding of digital design fundamentals

Additional Preferred Qualifications:

Experience with assertion-based verification (SVA)
Exposure to performance modeling and traffic generation
Exposure to emulation platforms (e.g., Palladium, Veloce) a plus
Scripting skills (Python/Perl/Shell)
Experience with low-power verification (UPF)

Develop and execute verification plans for high-speed memory interfaces (PCIE 6/7, CXL 3.2/4.0)
Build and enhance UVM/System Verilog-based verification environments
Develop test benches, sequences, and checkers for functional and performance validation
Perform protocol-level verification for PCIE controllers and PHY interfaces
Analyze and debug simulation failures, identify root causes, and drive resolution
Work closely with design, architecture, and firmware teams to ensure coverage closure and spec compliance
Contribute to coverage-driven verification (CDV) including functional, code, and assertion coverage
Support emulation/FPGA validation and post-silicon bring-up (nice to have)
Review design specifications and provide feedback for testability and robustness

Expected Base Pay Range (USD)

135,900 - 201,130, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Senior Staff Design Verification Engineer – PCIE/CXL Sub-System